Power supply clamps are used for ESD protection in complementary metal oxide semiconductor (CMOS) circuits. FIG. 1 depicts a common ESD protection circuit 10 for an integrated circuit consisting of a resistor-capacitor (RC) time constant network 12 composed of a resistor 14 and a capacitor 16. The RC time constant network 12 is connected to an inverter 18, which in turn drives a transistor array 20 to clamp the power supply to ground during the ESD event. The ESD protection circuit 10 is designed to stay on only long enough to dissipate the ESD pulse and then turn off again. The length of time that the ESD protection circuit 10 is on is controlled by the RC time constant connected to the inverter 18. One notable feature of the ESD protection circuit 10 is that each time the integrated circuit is powered up, a current spike occurs while the clamp is on prior to the RC trigger timing out. For most applications, this short surge of current is purely incidental and is not detrimental to the functioning of the integrated circuit.
However, the ESD protection circuit 10 may also turn on when voltage transients cause large enough swings on the supply rails. If these voltage transients are inherent to an application, for example with dc to dc buck converters, the transistor array 20 can stay on indefinitely, which draws down the power rail. Another scenario where the ESD protection circuit 10 may be problematic is when the power supply is current limited such that the power supply is drawn down when the transistor array 20 turns on momentarily at startup of the integrated circuit. When the RC time constant releases, the voltage suddenly spikes up. At this point, the clamp may turn on again and a recurring oscillation ensues.
Thus, there is a need for a new ESD clamp circuit that is insensitive to the transients produced on the power rail of an integrated circuit.